Design of Ultra High Speed ADC Data Receiving Based on LVDS

Abstract: ultra high speed ADC usually uses LVDS level to transmit data. High sampling rate makes the output data rate very high, reaching the order of 100 megahertz to gigahertz. How to correctly receive high-speed LVDS data has become a difficulty. Taking the data reception of ads42lb69 chip as an example, this paper details the problems that should be paid attention to and the specific implementation method of LVDS data reception from the two aspects of signal transmission and data decoding, and carries out experimental tests to verify the correctness of the method.

1 Introduction

The concept of software radio requires the digitization of radar system to be as close to the antenna as possible, so the digital receiving system puts forward high requirements for the rate of analog-to-digital converter. High speed and high precision ADC will output multi bit high-speed data stream. At present, the mainstream data transmission level is low voltage differential signal (LVDS). The differential transmission characteristics of LVDS make the electromagnetic interference produced by LVDS very small. It can also effectively suppress the common mode noise and increase the anti-interference ability. With the increase of data rate, the time window of multi-channel data synchronous reception becomes smaller. How to ensure the correct reception of multi-channel data has become a design difficulty. In order to reduce this difficulty, ADC devices generally adopt serial mode and use fewer data lines to complete the transmission of multi bit sampling data. Aiming at the problem of multi bit high-speed LVDS data transmission, this paper studies the method to realize the correct reception of LVDS data. Taking ads42lb69 as an example, a set of data acquisition board based on Xilinx FPGA platform is designed and verified by experiments. Next, the problems needing attention in the design and specific implementation methods are introduced in detail from the two aspects of signal transmission and data decoding.

2 signal transmission

In order to receive data correctly, it is necessary to ensure the integrity of signal transmission, reduce distortion and enable the receiver to correctly obtain serial LVDS data. Signal integrity can be divided into timing, noise and electromagnetic interference. For high-speed digital signal transmission, signal integrity includes waveform integrity and timing integrity.

2.1 waveform integrity

Waveform integrity refers to the influence of the transmission line on the electrical performance of the signal, such as voltage, current and power. There are three main noise sources affecting waveform integrity: signal integrity of a single network, crosstalk between two or more networks, and electromagnetic interference and radiation from the system. For each noise source, it needs to be solved in different ways in the design.

The first kind of problem refers to the reflection and distortion caused by impedance discontinuity on the signal transmission path. Equation (1) gives the relationship between the reflection coefficient of the RF transmission line and the transmission line impedance (where, γ Is the reflection coefficient, is the load impedance, and ZL is the characteristic impedance of the transmission line). It can be seen from the formula that when the load impedance is equal to the characteristic impedance of the transmission line, the reflection coefficient is zero, and the signal can be transmitted without distortion. Therefore, in order to ensure the integrity of signal waveform, the transmission line impedance is required to be continuous, and the receiver impedance should be accurately matched. Transmission line impedance continuity requires special design during PCB wiring, including 100 Ω impedance control for differential signal line, data line routing on the same layer as far as possible, reference plane continuity, etc. Load impedance matching is achieved by placing a 100 Ω resistor at the receiving end. In order to reduce the difficulty of layout, Xilinx FPGA integrates matching resistance, and the resistance value can be configured according to the application requirements.

When there is mutual inductance or mutual capacitance between the signal transmission path and adjacent networks, the signal will arrive from one network to another, resulting in crosstalk between networks. In order to reduce such problems, the distance between adjacent signal lines shall be far and the line length shall be as short as possible during PCB wiring. The electromagnetic interference of the system needs to be considered in the system design to reduce the radiation of various components, so as to reduce the electromagnetic interference.

2.2 timing integrity

The sampled data is transmitted through multiple pairs of LVDS differential lines, latched at the receiving end at the same time, and recovered after serial parallel conversion and data rearrangement. Usually, ADC chip will output high-speed data synchronization clock and frame clock for data latch, serial parallel conversion and decoding. The receiving end locks the data on all signal lines at the same time. In order to ensure that the receiving end obtains the data correctly, it is required to make the delay of each transmission line as same as possible. In order to ensure the consistent delay of transmission lines, it is necessary to make equal length constraints on all data lines and frame clock wiring in PCB. Due to the limitation of the accuracy of the board and welding process, the delay of the data lines on the final circuit board will still be different. At this time, signal delay should be adjusted in FPGA to ensure timing integrity. Possible timing integrity problems include several types:

1) The delay value of a bit data line is too large or too small, resulting in that the data bits transmitted on this line are not from the same sampling data as other data bits. At this time, the data line delay can be adjusted through the iodelay module in FPGA.

2) There is a big difference between the frame clock and the data line delay, resulting in the data can not be decoded correctly. Similarly, the iodelay core (FPGA) can be inserted into the transmission path of this line to adjust the delay.

3) The delay difference between the synchronization clock and the data line is large. When the data does not meet the establishment and holding time, it cannot be received correctly. There are two ways to solve this problem: one is to adjust the clock line delay through iodelay module, and the other is to change the phase of the PLL output clock.

3 data decoding

After ensuring the integrity of signal transmission and obtaining correct serial data, serial parallel conversion and data reorganization are also needed to obtain the final sampling data. This process is realized in FPGA. Ads4 2lb69 supports 4-wire (Lane) serial transmission. Each lane transmits 4bit data. The program structure of receiving this ADC data in FPGA is shown in Figure 1. The serial data lane and the frame clock (frame) are first subjected to 1:4 serial parallel conversion. The data lane corresponds to the 4-bit data register level, and then outputs 8-bit data (where the low 4-bit is the data d0 at one time and the high 4-bit is the data D1 locked at the next time), and then obtains the correct 4-bit data from the 8-bit register data according to the 4-bit frame data, Finally, four groups of 4-bit data are rearranged according to the sequence in the ADC manual to obtain 16 bit sampling data.

1: 4. Serial parallel conversion is completed by iserdes core inside FPGA. Since the time when iserdes core starts serial parallel conversion is uncertain, the converted 4-bit parallel frame data has four values corresponding to different data bit acquisition, as shown in Figure 2.

4 experimental verification

In order to verify the correctness of multi bit LVDS data receiving design, the data acquisition board is tested in the laboratory. The signal source is used to simulate the input signal and sampling clock, and the rearranged sampling data in FPGA is uploaded to PC through JTAG test interface and displayed in chipscope software. Fig. 3 shows the test results when the sampling clock is 180mhz and the input signal frequency is 10MHz, where frame_ Ilatst is the frame clock data used to obtain data bits, and data is the timing waveform of sampling data. It can be seen from the figure that the waveform is a single frequency point sine wave, which proves the correctness of the design.

5 Conclusion

The correct reception of LVDS data of overspeed ADC is very important for digital receiver. This paper describes how to realize the correct reception of multi bit high-speed LVDS data from two aspects of theoretical analysis and design and implementation. The data acquisition board is designed with Xilinx FPGA and ads42lb69, and the data receiving program is realized in FPGA. The experimental test shows that the hardware and program design can receive the sampling data correctly. The method in this paper has certain guiding significance for similar ADC data receiving design.

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