Power Supply Design

Power supply design

Key words: power supply design

Figuring out how much capacitance and resistance to add is a challenging task. Here is a shortcut to solve this problem. Figure 1 shows the power stage of the forward converter. The converter is operated by a transformer, which couples the input voltage to the secondary circuit, and then the secondary circuit rectifies and filters the input voltage. The reflected main voltage and transformer leakage inductance form a low impedance circuit. When D2 is forced to commutate off through such a resistance, a buffer is usually required. D2 can be a silicon p-n diode with a reverse recovery charging function that must be exhausted before it is turned off. This loads up the excess current in the leakage inductance, resulting in high-frequency ringing and excessive diode voltage. A similar situation exists between Schottky diode and synchronous rectifier. The former is due to its large junction capacitance and the latter is due to its shutdown delay time. Figure 1 shows that the leakage inductance delays the closing of D2, and Figure 2 shows some circuit waveforms. The top trace is Q1 leakage voltage, the middle trace is the voltage at the nodes D1 and D2, and the bottom trace is the current flowing through D1. In the top trace, you can see that when Q1 is turned on, its leakage voltage is reduced below the input voltage, which increases the current of diode D1. If D2 has no reverse recovery charging function, when D1 current is equal to the output current, the node voltage will rise. Since D2 has the reverse recovery charging function, the D1 current will further increase, which begins to consume charge. Once the charge is exhausted, the diode turns off, resulting in a further increase in the increased node voltage. Note that the current will continue to increase until the node voltage is equal to the reflected input voltage, because there is a positive voltage at both ends of the leakage inductance. As the current increases, the current will charge the parasitic capacitance and cause ringing and greater loss in the circuit. Fig. 2 when D2 is turned off, D2 will cause too many ringing waveforms. These ringing waveforms may be unacceptable because they will cause EMI problems or unacceptable voltage stress on the diode. The RC buffer across D2 can greatly reduce ringing without affecting efficiency. You can calculate the ringing frequency using the following equation (see equation 1): equation 1: but how do you know the values of L and C in the circuit? The trick is to reduce the ringing frequency by adding a capacitor with a known capacitance value at both ends of D2, so you get two equations and two unknown terms. If you add a capacitor that can just halve the ringing frequency, it will make it easier to find the above value. To reduce the frequency by half, you need a total capacitance of 4 times the parasitic capacitance you first used. Then, the parasitic capacitance can be obtained by dividing the added capacitance by 3. Fig. 3 shows the waveform of 470pf capacitance at both ends of D2 when the frequency is half of the initial ringing frequency. Therefore, the circuit has a parasitic capacitance of about 150 PF. Note that only adding capacitance has little effect on the amplitude of the ring, and the circuit also needs some resistance to damp the ring. This is another reason why capacitance factor 3 is a good place to start. If the selected resistance is appropriate, it can provide excellent damping effect with minimal impact on efficiency. The optimum value of damping resistance is almost the typical resistance of parasitic elements (see equation 2). Equation 2: Figure 3 increases the ringing frequency by twice to complete the parasitic calculation. Using equation 1 with 35MHz ringing frequency and a parasitic capacitance of 150pF, the leakage inductance can be calculated as 150nh. Substituting 150 NH into equation 2 yields a buffer resistance of approximately 30 ohms. Figure 4 shows the effect of adding buffer resistance. The ringing is completely eliminated and the voltage stress is reduced from 60V to 40V. In this way, we can select a diode with lower rated voltage to improve efficiency. The last step in this process is to calculate the buffer resistance loss. The last step of the process can be completed using equation 3, where f is the operating frequency: equation 3: once the calculation is completed, you need to determine whether the circuit can withstand the loss in the buffer. If not, you need to balance ringing and buffer loss. For details on how to select the best damping resistance, see Figure 3 Power Design Tips 4 on page 3. Fig. 4 selecting an appropriate buffer resistor can completely eliminate the ringing. In short, the buffered forward converter is a simple process: 1) adding capacitance to halve the ringing frequency; 2) Calculate parasitic capacitance and inductance; 3) Calculate the damping resistance and inductance 4) to determine whether the circuit loss is within the acceptable range.

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